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SY89846U
1.5GHz Precision, LVPECL 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination
General Description
The SY89846U is a 2.5/3.3V, 1:5 LVPECL fanout buffer with a 2:1 differential input multiplexer (MUX). A unique Fail-Safe Input (FSI) protection prevents metastable output conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops significantly below 100mV). The differential input includes Micrel's unique, 3-pin internal termination architecture that can interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. The outputs are 800mV, LVPECL with fast rise/fall times guaranteed to be less than 250ps. The SY89846U operates from a 2.5V 5% or 3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. The SY89846U is part of Micrel's high-speed, Precision Edge(R) product line. All support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge(R)
Features
* Selects between two inputs, and provides 5 precision LVPECL copies * Fail-Safe Input - Prevents outputs from oscillating when input is invalid * Guaranteed AC performance over temperature and supply voltage: - DC-to >1.5GHz throughput - < 900ps Propagation Delay (IN-to-Q) - < 250ps Rise/Fall times * Ultra-low jitter design: - <1psRMS random jitter - <1psRMS cycle-to-cycle jitter - <10psPP total jitter (clock) - <0.7psRMS MUX crosstalk induced jitter * Unique, patented MUX input isolation design minimizes adjacent channel crosstalk * Unique patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) * Wide input voltage range. VCC to GND * 2.5V 5% or 3.3 10% supply voltage * -40C to +85C industrial temperature range * Available in 32-pin (5mm x 5mm) MLF(R) package
Functional Block Diagram
Applications
* Fail-safe clock protection * SONET clock distribution * Backplane distribution
Markets
* * * * LAN/WAN Enterprise servers ATE Test and measurement
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
March 2007
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Micrel, Inc.
SY89846U
Ordering Information(1)
Part Number SY89846UMG SY89846UMGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals Only. 2. Tape and Reel.
Package Type MLF-32 MLF-32
Operating Range Industrial Industrial
Package Marking SY89846U with Pb-Free bar-line Indicator SY89846U with Pb-Free bar-line Indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
32-Pin MLF(R) (MLF-32)
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SY89846U
Pin Description
Pin Number 1,8 Pin Name VT0, VT1 Pin Function Input Termination Center-Tap: Each side of a differential input pair terminates to the VT pin. The VT pin provides a center-tap for each input (IN, /IN) to a termination network for maximum interface flexibility. See "Input Interface Applications" subsection. Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC- or DC-coupled signals as small as 100mV. The input pairs internally terminate to a VT pin through 50. Each input has level shifting resistors of 3.72k to VCC. This allows a wide input voltage range from VCC to GND. See Figure 3a, Simplified Differential Input Stage for details. Note that these inputs will default to a valid (either HIGH or LOW) state if left open. See "Input Interface Applications" subsection. Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pins. Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q4 outputs. It is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. When disabled, Q goes LOW and /Q goes HIGH. OE being synchronous, outputs will be enabled/disabled following a rising and a falling edge of the input clock. VTH = VCC/2. Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. VTH = VCC/2. Reference Voltage: These outputs bias to VCC-1.2V. They are used for ACcoupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01F low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is 0.5mA. See "Input Interface Applications" subsection. Positive Power Supply: Bypass with 0.1F||0.01F low ESR capacitors as close to the VCC pins as possible. LVPECL Differential Output Pairs: Differential buffered output copies of the selected input signal. The output swing is typically 800mV. Unused output pairs may be left floating with no impact on jitter. See "LVPECL Output Termination" subsection. Normally terminated with 50 to VCC-2V. These differential LVPECL outputs are a logic function of the IN0, IN1, and SEL inputs. See "Truth Table" below.
2, 3 6, 7
IN0, /IN0 IN1, /IN1
10, 11, 30, 31
GND, Exposed Pad
4
OE
5
SEL
9, 32
VREF-AC1 VREF-AC0
12, 13, 16, 19, 22, 25, 28, 29 27, 26 24, 23 21, 20 18, 17 15, 14
VCC Q0, /Q0 Q1, /Q1 Q2, /Q2 Q3, /Q3 Q4, /Q4
Truth Table
Inputs IN0 0 1 X X /IN0 1 0 X X IN1 X X 0 1 /IN1 X X 1 0 SEL 0 0 1 1 Outputs Q 0 1 0 1 /Q 1 0 1 0
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SY89846U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) .......................... -0.5V to +4.0V Input Voltage (VIN) ..................................-0.5V to VCC LVPECL Output Current (IOUT) Continuous ................................................. 50mA Surge........................................................ 100mA Current (VT) Source or sink on VT pin........................ 100mA Input Current Source or sink current on (IN, /IN) ........... 50mA Current (VREF) Source or sink current on VREF-AC(4) ......... 0.5mA Maximum operating Junction Temperature .....125C Lead Temperature (soldering, 20sec.) .............260C Storage Temperature (Ts)................-65C to +150C
Operating Ratings(2)
Supply Voltage (VCC) ..................+2.375V to +2.625V .....................................................+3.0V to +3.6V Ambient Temperature (TA)................ -40C to +85C Package Thermal Resistance(3) MLF(R) ( JA) Still-Air ..................................................... 50C/W MLF(R) ( JB) Junction-to-Board .................................... 31C/W
DC Electrical Characteristics(5)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RIN RDIFF_IN VIH VIL VIN VDIFF_IN VIN_FSI VREF-AC VT_IN
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still air unless otherwise stated. 4. Due to the limited drive capability, use for input of the same package only. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIN (max) is specified when VT is floating.
Parameter Power Supply Voltage Power Supply Current Input Resistance (IN-to-VT) Differential Input Resistance (IN-to-/IN) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing |IN-/IN| Input Voltage Threshold that Triggers FSI Output Reference Voltage Voltage from Input to VT
Condition
Min 2.375 3.0
Typ 2.5 3.3 60
Max 2.625 3.6 75 55 110 VCC VIH-0.1 1.0
Units V V mA V V V V
No load, max VCC 45 90 0.1 0 See Figure 2a. Note 6 See Figure 2b. 0.1 0.2
50 100
30 IVREF-AC = + 0.5mA VCC-1.3 VCC-1.2
100 VCC-1.1 1.28
mV V V
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SY89846U
LVPECL Outputs DC Electrical Characteristics(7)
VCC = 2.5V 5% or 3.3V 10%; RL = 50 to VCC-2V; TA = -40C to + 85C, unless otherwise stated.
Symbol VOH VOL VOUT VDIFF_OUT Parameter Output HIGH Voltage Output LOW Voltage Output Voltage Swing Differential Output Voltage Swing Condition Q, /Q Q, /Q See Figure 2a. See Figure 2b. Min VCC-1.145 VCC-1.945 550 1100 800 1600 Typ Max VCC-0.895 VCC-1.695 950 Units V V mV mV
LVTTL/CMOS DC Electrical Characteristics(7)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
-125 -300
30
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SY89846U
AC Electrical Characteristics(8)
VCC = 2.5V 5% or 3.3V 10%; RL = 50 to VCC-2V; Input tr/tf < 300ps; TA = -40C to + 85C, unless otherwise stated.
Symbol fMAX tpd Parameter Maximum Operating Frequency Differential Propagation Delay IN-to-Q IN-to-Q SEL-to-Q tSKEW Output-to-Output Skew Input-to-Input Skew Part-to-Part Skew tJITTER Clock Random Jitter Cycle-to-Cycle Jitter Total Jitter Crosstalk-Induced Jitter tr, tf Output Rise/Fall Time (20% to 80%) Duty Cycle
Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. Propagation delay is measured with input tr, tf 300ps (20% to 80%). The propagation delay is a function of the rise and fall times at IN. See "Typical Operating Characteristics" for details. 10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold do not apply. 11. Output-to-Output skew is measured between two different outputs under identical transitions. 12. Input-to-Input skew is the time difference between the two inputs to one output, under identical input transitions. 13. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 14. Random Jitter is measured with a K28.7 character pattern, measured at 12
Condition VOUT 400mV, VIN 200mV VOUT 400mV, VIN 100mV 100mV < VIN 200mV, Note 9 200mV < VIN 800mV, Note 9 VTH = VCC/2 Note 11 Note 12 Note 13 Note 14 Note 15 Note 16 Note 17 At full output swing. VIN > 200mV 100mV < VIN 200mV
Min 1.5 1.0 600 400 350
Typ 2.0 1.5 850 700 600 7 5
Max
Units GHz GHz
1100 900 800 20 15 300 1 1 10 0.7
ps ps ps ps ps ps psRMS psRMS psPP psRMS ps % %
110 47 45
170
250 53 55
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SY89846U Input Clock Failure Case If the input clock fails to a floating, static, or extremely low signal swing such that the voltage swing across the input pair is significantly less than 100mV, FSI function will eliminate a metastable condition and latch the outputs to the last valid state. No ringing and no undetermined state will occur at the output under these conditions. The output recovers to normal operation once the input signal returns to a valid state with a typical swing greater than 30mV. Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to "Typical Operating Characteristics" for detailed information. Output Enable (OE) OE is a synchronous TTL/CMOS compatible input that enables/disables the outputs based on the input to this pin. The enable function is synchronous so that the clock outputs will be enabled or disabled following a rising and a falling edge of the input clock. Refer to Figure 1c. Internal 25k pull-up resistor defaults the input to logic HIGH if left open. Input switching threshold is VCC/2.
Functional Description
Clock Select (SEL) SEL is an asynchronous TTL/CMOS compatible input that selects one of the two input signals. An internal 25k pull-up resistor defaults the input to logic HIGH if left open. Input switching threshold is VCC/2. Refer to Figure 1a. Fail-Safe Input (FSI) The input includes a special fail-safe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mVPK (200mVPP), typically 30mVPK. Maximum frequency of the SY89846U is limited by the FSI function. Refer to Figure 1b.
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SY89846U
Timing Diagrams
Figure 1a. SEL-to-Q Delay
Figure 1b. Fail Safe Feature
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SY89846U
Figure 1c. Enable Output Timing Diagram
Figure 1d. Propagation Delay
Figure 1e. Setup and Hold Time
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SY89846U
Typical Operating Characteristics
VCC = 3.3V, GND = 0V, tr / tf 300ps, VIN = 100mV, RL = 50 to VCC-2V; TA = 25C, unless otherwise stated.
March 2007
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SY89846U
Functional Characteristics
VCC = 3.3V, GND = 0V, VIN 400mV, tr/tf 300ps, RL = 50 to VCC-2V; TA = 25C, unless otherwise stated.
March 2007
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SY89846U
Single-Ended and Differential Swings
Figure 2a. Single-Ended Voltage Swing
Figure 2b. Differential Voltage Swing
Input and Output Stages
Figure 3a. Simplified Differential Input Stage
Figure 3b. Simplified Differential Output Stage
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SY89846U
Input Interface Applications
Option: may connect VT to VCC Figure 4a. LVPECL Interface (DC-Coupled) Figure 4b. LVPECL Interface (AC-Coupled) Figure 4c. CML Interface (DC-Coupled)
Figure 4d. CML Interface (AC-Coupled)
Figure 4e. LVDS Interface (DC-Coupled)
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SY89846U
PECL Output Interface Applications
PECL has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low EMI. PECL is ideal for driving 50- and 100-controlled impedance transmission lines. There are several techniques for terminating the PECL output: parallel termination-thevenin equivalent, parallel termination (3-resistor), and ACcoupled termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.
Figure 5b. Parallel Termination (3-Resistor)
Figure 5a. Parallel Termination-Thevenin Equivalent
Related Product and Support Documentation
Part Number SY89847U Function Precision LVDS 1 :5 Fanout with 2 :1 MUX and Fail-Safe Input with Internal Termination MLF(R) Application Note HBW Solutions New Products and Applications Data Sheet Link www.micrel.com/product-info/products/sy89847u.shtml. www.amkor.com/products/notes_papers/MLFAppNote.pdf www.micrel.com/product-info/products/solutions.shtml
March 2007
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Micrel, Inc.
SY89846U
Package Information
32-Pin (5mm x 5mm) MLF(R)
Packages Notes: 1. 2. 3. Package meets Level 2 Moisture Sensitivity Classification. All parts are dry-packed before shipment. Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Inc.
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